View U6239B_223348.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

U6239B
2.9 GHz PLL for SAT TV Tuner with UNi-Bus
Description
The U6239B is a single-chip frequency synthesizer with bidirectional I2C bus control and unidirectional 3-wire bus control, developed for SAT TV-tuner and cable tuner applications. This IC contains an integrated preamplifier, a high frequency prescaler, a reference divider with multiple programmable divider ratios, a crystal oscillator, a phase/ frequency detector together with a charge pump, a tuning amplifier and an analog-to-digital converter.
Features
D 2.9 GHz divide-by-16 prescaler integrated D UNi-BUS:
I2C bus and 3-wire bus I2C bus software compatible to U6223B 3-wire bus software compatible to LC7215 (Sanyo) 4 bidirectional ports (open collector) 2 unidirectional ports (open collector) 5 level ADC or unidirectional port (open collector) Address mode select function (AMS, Pin 3): 3 or 4 addresses selectable via Pin 10
D 3-wire bus mode:
4 unidirectional ports (open collector) Lock output (open collector)
D I2C bus mode:
D Programmable reference divider D Low power consumption (typ. 5 V / 23 mA) D Electrostatic protection according to MIL-STD 883
Block Diagram
AS / ENABLE / P3 10 SCL 5 SDA 4 UNI-BUS Control
11 P0/Lock 5-bit Latch ADC I/O Ports 7-bit Latch 8-bit Latch 7-bit Latch T1 9 P4 8 P5 7 P6 / ADC 6 P7
Vs 12 GND 15
Power-on reset
POR 14-bit Shift Reg.
Sync
15-bit Latch LOCK
T0
5I
RD1,2,3
OS
AMS RFi 14 13 div. by 16 Prescaler
SET 15/14-bit counter RDS divide by 256/512/off/1024 divide by 25/50/140/250 divide by 50/100/280/500 Phase detector Charge pump FR FP
RDS / AMS 3 XTAL 2 Oscillator
16 VD 1 PD
9611809
Figure 1.
Rev. A4, 20-Apr-99
1 (15)
U6239B
Ordering Information
Extended Type Number U6239B-CFPG3 Package SO16, plastic package Remarks Taped and reeled SSO16 package on request
Pin Configuration
PD Q1 1 2 16 15 14 13 12 11 VD GND RFi RFi VS P0/ Lock
RDS/AMS 3 SDA SCL P7 P6/ ADC P5 4 5 6 7 8
95 10947
10 AS/ENABLE/ P3 9 P4
Circuit Description
The U6239B is a single-chip PLL designed for SAT TV tuner and cable tuner. It consists of a divide-by-16 prescaler with an integrated preamplifier, a 15-bit programmable divider, a crystal oscillator, and a reference divider with selectable divider ratios, a phase/ frequency detector together with a charge pump which drives the tuning amplifier. Only one external transistor is required for varactor line driving. The device can be controlled via I2C bus format or via 3-wire bus format. It detects automatically which bus format has been received. Therefore, there is no need for a bus selection pin. In I2C bus mode, the device has four programmable or one fixed and three programmable I2C bus addresses, depending on the voltage level at Pin 3. They are
2 (15)
A A AAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAA A AA AA A AAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AA AA A AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAA A A AAAAAAAAAAAAAAAA AA AAAAAAAAAA A AAAAAAAAAA A A AA AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAA A A AAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAA A AA AAAAAAAAAAAAAAAA AAAAAAA A
4 5 6 7 8 9 10 11 12 13 14 15 16 SDA SCL P7 P6/ ADC P5 P4 AS/ ENABLE/ P3 P0/Lock VS RFi RFi GND VD programmed by applying a specific input voltage to the address select input Pin 10, enabling the use of up to four synthesizers in a system. If the fixed address is used, this pin can be used as a normal output port. The same pin serves as the enable signal input in 3-wire bus mode. Depending whether the fixed address is used or not there are five or six open collector outputs for switching functions available. In 3-wire bus mode there are four open collector outputs and one lock signal output. All open collector outputs are capable of sinking at least 10 mA. In I2C bus mode an analog-to-digital converter (ADC) is available for digital AFC (automatic frequency control) applications and the ports P4, P5 and P7 can also be used as input ports. Rev. A4, 20-Apr-99
Pin 1 2 3
Symbol PD Q1 RDS/ AMS
Function Charge pump output Crystal input Reference divider select input (3-wire bus mode) Address mode select input (I2C bus mode) Data input/ output Clock input Port 7 input/ output Port 6 output Analog-Digital-Converter input Port 5 input/ output Port 4 input/ output Address select input Enable input Port 3 output Port 0 output/Lock output Supply voltage RF input RF input Ground Active filter output
U6239B
Functional Description
The U6239B is programmed via a 2-wire I2C bus or 3-wire bus depending on the received data format. In I2C bus mode the three bus input pins 4, 5, 10 are used as SDA, SCL and address select inputs or in 3-wire bus mode as date, clock and enable inputs, respectively. The data include the scaling factor SF and port output information. In I2C bus mode there are some additional functions available (ADC, bidirectional ports, etc.) Oscillator frequency calculation : fVCO = 16 fvco: SPF frefosc/SRF prescaler input sensitivity"). The input impedance is shown in the diagram "Typical input impedance". When a new divider ratio is entered according to the requested fVCO, the phase detector and charge pump adjusts the control voltage of the VCO together with the tuning amplifier until the output signals of the programmable divider and the reference divider are in frequency locked and phase locked. The reference frequency may be provided by an external source, capacitively coupled into Pin 2, or by using an on-board crystal with an 18 pF capacitor in series. The crystal operates in the series resonance mode. The reference divider division ratio is selectable to in the I2C bus mode and in the 3-wire bus mode.
Locked frequency of voltage controlled oscillator
SPF : Scaling factor of programmable divider (15 bit in I2C bus mode, 14 bit in 3-wire bus mode) SRF : Scaling factor of reference divider (B256 in I2C bus mode, in 3-wire bus mode)
B500
B256/ B512/ B1024 B25/ B50/ B100/ B140/ B250/ B280/
B512/B1024 B25/B50/B100/B140/B250B280/B500
In I2C bus mode, the division ratio may be set via three bits, in 3-wire bus mode via two bits and a voltage at the reference divider select input Pin 3. In addition, there are port outputs available for band switching and other purposes.
Application
A typical application is shown on page 14. All input/ output interface circuits are shown on the pages 12 and 13. Some special features which are related to test- and alignment procedures for tuner production are explained together with the bus mode descriptions.
frefosc: Reference oscillator frequency: 3.2/ 4 MHz crystal or external reference frequency (max. 8 MHz) The input amplifier together with a divide-by-16 prescaler provides excellent sensitivity (see "Typical
Absolute Maximum Ratings
All voltages are referred to GND (Pin 15)
AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A AA A AA AA AA AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA AA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A A A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAA A A AAAA A A A A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA
Pin 12 Pins 13, 14 Pins 6-11 Pins 6-11 Pins 6-10 Pins 6-11 Pins 4 and 5 Pin 4 Pin 10 Open collector Open collector In off state In on state SDA output current Address select/ Enable input Port output voltage Open collector Port in off state -1 -0.3 5 14 mA V Charge pump output voltage Active filter output voltage Crystal oscillator voltage Reference divider select input/ Address mode select input Junction temperature Storage temperature Pin 1 Pin 16 Pin 2 Pin 3 -0.3 -0.3 -0.3 -0.3 -40 -40 Vs + 0.3 Vs + 0.3 Vs + 0.3 VS + 0.3 125 125 V V V V C C Rev. A4, 20-Apr-99 3 (15)
Parameters Supply voltage RF input voltage Port output current Total port output current Port input/ output voltage Port output voltage Bus input/ output voltage
Symbol Vs RFi P0, P3-7 P0, P3-7 P3-7 P0, P3-7 VSDA, VSCL ISDA AS/ ENABLE/ P3 PD VD Q1 RDS/ AMS Tj Tstg
Conditions
Min. -0.3 -0.3 -1 -1 -0.3 -0.3 -0.3
Max. 6 Vs + 0.3 15 50 14 6 6
Unit V V mA mA V V V
U6239B
Operating Range
All voltages are referred to GND (Pin 15)
AAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A AA AA A A AA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAA A A A A AA AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A
AAAA A A A A A A AAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A
Pins 13 and 14 I2C bus mode 3-wire bus mode
Parameters Supply voltage Ambient temperature Input frequency Programmable divider Programmable divider
Test Conditions / Pins Pin 12
Symbol VS Tamb RFi SF SF
Min. 4.5 -20 250 256 256
Typ. 5
Max. 5.5 85 2900 32767 16383
Unit V C MHz
Thermal Resistance
Parameters Junction ambient
Test Conditions / Pins Package SO16 soldered to PCB
Symbol RthJA
Min.
Typ. 110
Max.
Unit K/W
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 5 V, Tamb = 25C Parameters Test Conditions / Pins Symbol Min. Supply current (prescaler on) Ports off Pin 12 ICC Input sensitivity fRFi = 250 MHz Pin 13 Vi 1) 100 fRFi = 750 -2900 MHz Pin 13 Vi 1) 20 Crystal oscillator Recommended crystal series 10 resistance Crystal oscillator drive level Pin 2 Crystal oscillator source Nominal spread 15% impedance Pin 2 External reference input AC coupled sinewave 2 frequency Pin 2 External reference input AC coupled sinewave 70 amplitude Pin2 Port outputs (current limited, output function only in I2C bus mode) Port P0 at Pin 11. Port P3 at Pin 10, is only usable with AMS = `L' (= 3 address mode). P0, P3 Sink current VH = 12 V, Pins 10 and 11 ISL 0.7 Leakage current VH = 13.2 V IL Port outputs, Lock output (open collector, locked = `L'. Ports P4 - P7 at Pins 6-9) Lock output at Pin 11, only in 3-wire bus mode. Saturation voltage IL = 10 mA VSL 2) Leakage current VH = 13.2 V IL Port inputs (Ports 4, 5 and 7 at Pins 6, 8 and 9) Input voltage high Vi `H' 2.7 Input voltage low Vi `L' Input current high Vi `H' = 13.2 V Ii `H' Input current low Vi `L' = 0 V Ii `L' -10 Typ. 23 Max. Unit mA
300 300 200
mVrms mVrms
W W
"
50 -650
mVrms
8
MHz
200
mVrms
1
1.5 10
mA
mA mA mA mA
V V V
0.5 10
0.8 10
4 (15)
Rev. A4, 20-Apr-99
U6239B
Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol ADC input (ADC, Pin 7, see page 8 for ADC-levels) Input current high Vi `H' = 13.2 V Ii `H' Input current low Vi `L' = 0 V Ii `L' Charge pump output (PD) Charge pump current `H' 5I = 1, VPD = 1.7 V, Pin 1 IPDH Charge pump current `L' 5I = 0, VPD = 1.7 V, Pin 1 IPDL Charge pump leakage current T0 = 1, VPD = 1.7 V, Pin 1 IPDTRI Charge pump amplifier gain Pins 1 and 16 Bus inputs Data and Clock (SDA, SCL) I2C bus mode and 3-wire bus mode Input voltage high Pins 4 and 5 Vi `H' Input voltage low Pins 4 and 5 Vi `L' Input current high Vi `H' = VS, Pins 4 and 5 Ii `H' Input current low Vi `L' = 0 V, Pins 4 and 5 Ii `L' Output voltage SDA ISDA`L' = 3 mA, Pin 4 VSDA `L' (open collector) Bus input Enable, 3-wire bus mode (ENABLE, Pin 10) Input voltage high Pin 10 Vi `H' Input voltage low Pin 10 Input current high Vi `H' = VS, Pin 10 Input current low (RDS = `L') Vi `L' = 0 V, Pin 10 Input current low (RDS = `H') Vi `L' = 0 V, Pin 10 Address selection / port output (AS/P3, Pin 10) Input current low (AMS = L) Vi `L' = 0 V (3 address) Input current high (AMS = L) Vi `H' = 13.2 V (3 address) Input current low (AMS = H) Vi `L' = 0 V (4 address) Input current high (AMS = H) Vi `H' = VS (4 address) Reference divider select/Address mode select (RDS, AMS) Input voltage high Pins 4 and 5 Input voltage low Pins 4 and 5 Input current high Vi `H' = VS, Pins 4 and 5 Input current low Vi `L' = 0 V, Pins 4 and 5 Vi `L' Ii `H' Ii `L' Ii `L' Ii `L' Ii `H' Ii `L' Ii `H' Vi `H' Vi `L' Ii `H' Ii `L' Min. Typ. Max. 10 -10 Unit
mA mA mA mA
nA
"180 "50 "5
6400 3 5.5 1.5 10 0.4
-20
mA mA
V
V V
75% VS
VS + 0.3 V 1.0 10
V
-10 -100 -10 10 -100 10 3 5.5 1.5 10
mA mA mA mA mA mA mA mA mA
V V
V
-20
Notes: 1) RMS - voltage calculated from the measured available power on 50 W. 2) Tested with one port active. The collector voltage of an active port must not exceed 6 V.
Rev. A4, 20-Apr-99
5 (15)
U6239B
I2C Bus Description
Functional Description
When the U6239B is controlled via a 2-wire I2C bus format, then data and clock signals are fed into the SDA and SCL lines respectively. Depending on the LSB of the address byte, the device can either accept new data (write mode: LSB = 0) or send data (read mode: LSB = 1). Depending on the voltage at the address mode select input, the device has one fixed and three programmable or four programmable I2C bus addresses. The tables "I2C bus write data format" and "I2C bus read data format" describe the format of the data and show how to select the device addresses by applying the appropriate voltages at address select Pin 10 and the address mode select Pin 3. smooth frequency sweep for fine tuning AFC purposes. The table "I2C bus pulse diagram" provides some possible data transfer examples. In addition, the stop condition is not a must, the device may be programmed by using the start condition only. The programmable divider bytes PDB1 and PDB2 are stored in a 15-bit latch and control the division ratio of the 15-bit programmable divider. The control byte CB1 enables the controlling of the following special functions:
D 5I bit switches between low and high charge pump
current
D T1 bit enables divider test mode when it is set to
logic 1
Write Mode (Address byte LSB = 0)
When write mode is activated and the correct address byte is received, the SDA line is pulled low by the device during the acknowledge period. The SDA line is also pulled low during the acknowledge periods, when additional data bytes are programmed. After the address transmission (first byte), data bytes can be sent to the device. There are four data bytes requested to fully program the device. Once the correct address is received and acknowledged, the first bit of the following byte determines whether that byte is interpreted as byte 2 or 4; a logic 0 for divider information and a logic 1 for control and port output information. If byte 2 has been received, the device always expects byte 3 next. Likewise if byte 4 has been received, byte 5 is expected. Additional data bytes can be entered without the need to re-address the device until an I2C bus stop condition is recognized. This allows a Description Address byte Programmable divider, byte 1 Programmable divider, byte 2 Control byte 1 Control byte 2 MSB 1 0 n7 1 P7 1 n14 n6 5I P6
D T0 bit enables the charge pump to be disabled when
it is set to logic 1
D RD3, 2 and 1 - bits enable selection of the reference
divider ratio
D OS-bit disables the charge pump drive amplifier output when it is set to logic 1. The charge pump current can only be controlled in I2C bus mode. In 3-wire bus mode, the high charge pump current is always active. The OS-bit function disables the complete PLL function. This enables the tuner alignment by supplying the tuning voltage directly through the 30 V supply voltage of the tuner. The control byte CB2 programs the port outputs P0 and P3 - 7.
I2C Bus Data Format 0 0 0 n13 n12 n11 n5 n4 n3 T1AAAAX T0 P5 P4 P3 AS1 AS2 n10 n9 n2 n1 RD2AAA RD1 X X LSB 0 n8 n0 OS P0 A A A A A
AAAA A A AAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAA AAAAA AAAAAAAAAAAAAAAAAA AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAA AAAA AAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA
A = Acknowledge; X = not used n0 to n14 : T0, T1 : Scaling factor (SF) Test mode selection P0, 3 to 7: 5I : OS : Port outputs Charge pump current switch Output switch SF = 16384 n14 + 8192 n13 + SF - range: 256 to 32767 T1 = 1: divider test mode on, FP at Pin 6, FR at Pin 7 T0 = 1: charge pump disable P0, 3, 4, 5, 6, 7 = 1: port active 5I = 1: high current OS = 1: varicap drive disable ... + 2 n1 + n0 T1 = 0: divider test mode off T0 = 0: charge pump enable 5I = 0: low current OS = 0: varicap drive enable 6 (15) Rev. A4, 20-Apr-99
U6239B
I2C Bus Description (continued)
Reference divider selection RD1, RD2: RD2 0 0 1 1 RD1 0 1 0 1 Reference Divider Ratio 1024 off 256 512 Frequency Step Size* 62.5 kHz - 250 kHz 125 kHz Max. Operating Frequency* 2.047 GHz - 2.9 GHz 2.9 GHz
* when a 4MHz crystal is used Address selection AS1, AS2, AMS: AMS Voltage at Pin 3 < 0.8 V or open < 0.8 V or open < 0.8 V or open < 0.8 V or open > 2.4 > 2.4 > 2.4 > 2.4 AS1 0 0 1 1 0 0 1 1 AS2 0 1 0 1 0 1 0 1 Address C0 C2 C4 C6 C0 C2 C4 C6 Dec. Value 192 194 196 198 192 194 196 198 Voltage at Pin 10 0 to 10% VS always valid 40 to 60% VS 90% VS to 13.2 V 0 to 10% VS open 40 to 60% VS 90% VS to VS
Read Mode (Address byte LSB = 1)
After the address transmission (first byte), the status byte can be read from the device on the SDA line (MSB first). Data is valid on the SDA line during logic high of the SCL signal. The controller accepting the data has to pull the SDA line to low-level during all status-byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line to low-level during this period, the device will then release the SDA line to allow the controller to generate a STOP condition. The POR bit (power-on-reset) is set to a logic 1 when the supply voltage VS of the device has dropped below 3 V (at 25C) and also when the device is initially turned on. The POR bit is reset to a logic 0 when the read sequence is terminated by a STOP condition. When the POR bit is set high (at low VS), this indicates that all the programmed information is lost and the port outputs are all set to high impedance state. The FL bit indicates whether the loop is in phase lock condition (logic 1) or not (logic 0). If the ADC or the ports are to be used as inputs, the corresponding outputs must be programmed to a high impedance state (logic 1). The bits I2, I1 and I0 show the status of the I/O ports P7, P5 and P4 respectively. A logic 0 indicates a LOW level and a logic 1 a HIGH level (TTL levels). The bits A2, A1 and A0 represent the digital information of the 5-level ADC. This converter can be used to feed AFC information to the controller from the IF section of the receiver, as shown in the typical application circuit on page 14.
Rev. A4, 20-Apr-99
7 (15)
U6239B
I2C Bus Description (continued)
Description Address byte Status byte MSB 1 POR 1 FL 0 I2 I2C Bus Read Data Format 0 I1 0 I0 AS1 A2 AS2 A1 LSB 1 A0 A -
I2C Bus Pulse Diagram
Address byte /A/ 1.Byte /A/
SDA
SCL START 1 2 3 4 5 6 7 8 9 1... 8 9 1... 8 9 1... 8 9 1... 8 9 STOP
Data transfer examples START - ADR - PDB1 - PDB2 - CB1 - CB2 - STOP START - ADR - CB1 - CB2 - PDB1 - PDB2 - STOP START - ADR - PDB1 - PDB2 - CB1 - STOP START - ADR - PDB1 - PDB2 - STOP START - ADR - CB1 - CB2 - STOP START - ADR - CB1 - STOP Description START = Start condition ADR = Address byte PDB1 = Programmable divider byte 1 PDB2 = Programmable divider byte 2 CB1 = Control byte 1 CB2 = Control byte 2 STOP = Stop condition
8 (15)
AAAAAAAAAA AA A AAAAAAAAAAAAAAAA A AA AAAAAAAAAA AA A AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA A AA AA AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAA AAAAAAA AA
2.Byte /A/ 3.Byte /A/ 4.Byte /A/
9611811
AAAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA A A A A A A A A AAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA
POR : FL : I2, I1, I0 : A2, A1, A0 : Power-on reset flag: In-lock flag: Digital information of I/O-ports P7, P5 and P4 respectively Digital data of the 5-level ADC. POR = 1 on power on FL = 1, when loop is phase locked see next table A/D Converter Levels: A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Input voltage to ADC Pin 9 60% Vs to 13.2 V 45% to 60% Vs 30% to 45% Vs 15% to 30% Vs 0 V to 15% Vs Rev. A4, 20-Apr-99
U6239B
I2C Bus Description (continued)
I2C Bus Timing
t W STT
SDA
9611812
t S STT
SCL
t LOW
t HIGH
tR
tF
t S STP
t H STT
START CLOCK
t S DAT
t H DAT
STOP
DATACHANGE
Figure 2.
AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AA A
ms ms ms ms ms ms ms ms ms ms
0 1 1 1 1 1 1 0.25 0 kHz
Parameters Rise time SDA, SCL Fall time SDA, SCL Clock frequency SCL Clock `H' pulse Clock `L' pulse Hold time start Waiting time start Setup time start Setup time stop Setup time data Hold time data
Symbol tR tF fSCL tHIGH tLOW tH STT tW STT tS STT tS STP tS DAT tH DAT
Min.
Max. 15 15 100
Unit
3-Wire Bus Description
When the U6239B is controlled via a 3-wire bus format, then data, clock and enable signals are fed into the SDA, SCL and AS/ENABLE/P3 lines respectively. The diagram "3-wire bus pulse diagram" shows the data format. The data consist of a single word which contains the programmable divider (14 bit) and port information. Bit No. 15 of the programmable divider is always zero, when the 3-wire bus mode is active. The data is only clocked into the internal data shift register on the negative clock transition during the enable high period. During enable low periods the clock input is disabled. New data words are only accepted by the internal data latches from the shift register on a negative transition of the enable signal if exactly eigtheen clock pulses were sent during the high period of the enable. The data sequence and the timing is described in the following diagrams.
In 3-wire bus mode Pin 9 automatically becomes the lock-signal output. An improved lock detect circuit generates a flag when the loop has attained lock. `In lock' is indicated by a low impedance state (on) of the open collector output. In 3-wire bus mode the high charge pump current is always active. The charge pump current can only be controlled in I2C bus mode. The complete PLL function can be disabled by programming a normally not used division ratio of zero. This allows the tuner alignment by supplying the tuning voltage directly through the 33 V supply voltage of the tuner. In 3-wire bus mode the division ratio of the reference divider is controlled via information RD1, RD2 and the reference divider select input Pin 3.
Rev. A4, 20-Apr-99
9 (15)
U6239B
3-Wire Bus Description (continued)
Reference divider selection RD1, RD2, RDS: RDS Voltage at Pin 3 0 to 10% VS or open 0 to 10% VS or open 0 to 10% VS or open 0 to 10% VS or open 90 to 100% VS 90 to 100% VS 90 to 100% VS 90 to 100% VS * when a 4-MHz crystal is used RD2 0 0 1 1 0 0 1 1 RD1 0 1 0 1 0 1 0 1 Reference Divider Ratio 280 50 500 100 140 25 250 50 Frequency Step Size* 228.57 kHz 1280 kHz 128 kHz 640 kHz 457.14 kHz 2560kHz 256 kHz 1280 kHz Maximum Operating Frequency* 2.9 GHz 2.9 GHz 2.097 GHz 2.9 GHz 2.9 GHz 2.9 GHz 2.9 GHz 2.9 GHz
3-Wire Bus Pulse Diagram
4 Port bits/ 2 Ref.Div. bits P4 P5 RD1 RD2 P6 SDA SCL ENABLE
9611813
P7
MSB n13
14-bit scaling factor SF
LSB n0
Figure 3.
n0 to n13 P4 to P7 RD1, RD2
Scaling factor (SF) Port outputs Reference divider selection
SF = 8192 n13 + 4096 n12 + ... +2 n1 + n0 SF - Range: 256..16383 P4 - P7 = 1: port active see table above
3-Wire Bus Timing
Data Clock Enable TL TS TC TH TSL TT
9611880
LSB
Figure 4.
Parameters Setup time Enable hold time Clock width Enable setup time Enable between two transmissions Data hold time 10 (15)
AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A
Rev. A4, 20-Apr-99
Symbol TS TSL TC TL TT TH
Min. 2 2 2 10 10 2
Max.
Unit
ms ms ms ms ms ms
U6239B
Typical Prescaler Input Sensitivity
Vi (mVrms on 50 W) 1000
100
Operating window
10
1 0 500 1000 1500 2000 Frequency (MHz) 2500 3000 3500 4000
9611877
Typical Input Impedence
j 0.5j 2j
0.2j 4.0 GHz 3.5 GHz 0 0.2 0.5 3.0 GHz -0.2j 2.5 GHz 2.0 GHz -0.5j 1.5 GHz -j
Figure 5.
5j
1
2
5 100MHz 500 MHz
1
-5j
1 GHz -2j Z 0 = 50
9611878
Rev. A4, 20-Apr-99
11 (15)
U6239B
Input/ Output Interface Circuits
Vref Vs
1.5k RF1 RF2
1.5k Port
Vref
9611853
Figure 6. RF input
9611856
Figure 8. Ports P4, P5, P6, P7
60
2k PD
P3
Vs
AMS 125k 12k 375k AS / P3 ENABLE
VD OS (O/P Disable) 45k
Vref AMS
9611857
9611854
Figure 9. Address select/ Enable input/ Port output P3
Figure 7. Loop amplifier
12 (15)
Rev. A4, 20-Apr-99
U6239B
VS
Vs
SDA/SCL/RDS/AMS
3k
XTAL Q1
40 k 20 ACK
9611858
RDS/AMS only
SDA only
96 11855
Figure 10. SCL/SDA and RDS/AMS input
Figure 11. Reference oscillator
Vs
P0
Lock 12k Port P0/Lock
9611810
Figure 12. Port P0/ Lock output
Rev. A4, 20-Apr-99
13 (15)
U6239B
Application Circuit
SAT-Tuner f SAT AFC fIF fVCO
33V RDS/AMS 22k 22n
3 1 2
4 MHz 18 p ADC 1n
7 13
RFi
1n
14 12 15
Vs GND SDA from/to mC SCL AS / ENABLE / P3
39k
100n
16
U6239B
8 9 11
6
4 5 10
P7
P5
P4
P0 / Lock
100 p
9611879
Figure 13.
Package Information
Package SO16
Dimensions in mm
10.0 9.85 5.2 4.8 3.7
1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85
technical drawings according to DIN specifications
13036
1
8
14 (15)
Rev. A4, 20-Apr-99
U6239B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify TEMIC Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A4, 20-Apr-99
15 (15)

▲Up To Search▲

Price & Availability of U6239B

	To Download U6239B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .